Ok,
Time for a little bit of programming trickery – this one related to makefiles and the fun of VPATH. One of the projects I was working on used the VPATH feature to build the code for each version in a subdirectory. That meant that you can have one makefile for any version, and simply include the delta makefile which contained all the conditional compilation work. The problem with this is that you need to write the makefile carefully, otherwise you can’t take advantage of this feature.
When you write a makefile rule you end up with something resembling:
target: dep1.c dep2.h $(CC) $(CFLAGS) -o target dep1.c
The rule itself is fine, the problem is that the build command will mess up when executed on a relative path build. The make tool cannot change the target and dep1.c entries to match the locations of the files in the build command; It’s not been given the ability to parse shell scripts. You need to use the correct variable syntax.
Firstly, we never use the absolute target name in a build – that’s really effing stupid – after all if we change the name of the target every other entry needs changing. What we use is the $@ variable – this is expanded at run time to match the target name – it means less typing, and less chance of an error.
The Second change is to replace the dep1.c with $<, this means take the first dependency of the rule, and as this is a vpath substitutable entry, this gets replaced with wherever the dep1.c is found.
I’ve been experimenting with this on a linux box and it works exactly as advertised for the gmake. I’ve not tested it recently on Solaris for svr make, I know there is a different semantic to $lt; there.